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Multiprocessor Computer System

Multiple central processing units (CPU) that have full access to a single random-access memory (RAM) are present in a computer system that is referred to as multiprocessor.

Any application that is being processed by one of the multiple central processing units in a multiprocessor system will perceive the same standard virtual address space.

The only unusual property of a multiprocessor system is that a central processing unit can write some value into a memory word, and then when it reads that word back out, it can get some different value because another central processing unit has changed it. This is the only unusual property of a multiprocessor system.

Now, when everything is set up properly, this feature serves as the foundation for inter-processor communication. This is the process in which one central processing unit writes the data into memory and another reads the data out.

This post on "multiprocessors" is divided into the following sections:

Multiprocessor Hardware

Every central processing unit (CPU) in a multiprocessor has the ability to address all of the memory in the system. This is a property shared by all multiprocessors.

Additionally, certain multiprocessors have the additional property that every memory word can be read at the same rate as every other memory word in the system. These computers are also known as "Uniform Memory Access" (UMA) multiprocessors. The Non-Uniform Memory Access (NUMA) multiprocessors, on the other hand, do not have this property.

The following is a list of multiprocessors:

Now, let's move on to providing a concise explanation of all of the multiprocessor hardware systems mentioned above.

UMA Bus-Based SMP Architectures

The SMP architecture that is based on a UMA bus is the most straightforward multiprocessor design because it only uses a single bus.

Communication between multiple central processing units and one or more memory modules is handled by a single bus that all of these components share.

UMA Multiprocessors using Crossbar Switches

Even with the most effective caching, the utilization of a single bus places a cap on the size of a uniform memory access multiprocessor; consequently, a different kind of interconnection is required.

A crossbar switch is the most straightforward method for establishing a connection between n CPUs and k memories in a computer system.

Within telephone switching exchanges, crossbar switches have been utilized for many years to connect a group of incoming lines to a set of outgoing lines in an arbitrary manner. This practice has been carried out for many years.

UMA Multiprocessors using Multistage Switching Networks

The humble 2*2 switch multiprocessor design has the switch equipped with two inputs in addition to its two outputs. Any message that arrives on either of the lines that serve as input can be routed to either of the lines that serve as output.

There is an infinite number of possible configurations that can be used to build larger multistage switching networks using 2*2 switches.

NUMA Multiprocessors

On machines with non-uniform memory access (NUMA), all of the programs that require uniform memory access (UMA) will run without modification; however, the performance on a NUMA machine will be inferior to that of a UMA machine operating at the same clock speed.

In a nutshell, NUMA machines are distinguished by the presence of the following three qualities:

Since you are already familiar with the concept of multiprocessor operating systems from earlier lessons, let's move on to the next section and discuss how to synchronize multiple processors.

Multiprocessor Synchronization

It is often necessary for the central processing units in a multiprocessor system to synchronize with one another.

It is necessary to have the appropriate multiprocessor synchronization primitives.

In this scenario, the kernel code can simply disable interrupts before interacting with the critical kernel table if any process on a uni-processor system makes a system call that requires access to some critical kernel table. It is able to carry out its duties with the assurance that it will be able to complete them without interference from any other processes that might try to get their hands on the table before it is done.

Now, disabling interrupts on a multiprocessor system only has an effect on the central processing unit that is performing the disablement; other central processing units continue to run and are still able to touch the critical table.

As a result, a correct mutex protocol needs to be utilized there, and it needs to be respected by all of the central processing units, in order to ensure that mutual exclusion is effective.

Multiprocessor Scheduling

On a multiprocessor, scheduling is done in a two-dimensional space. The scheduler of a multiprocessor is responsible for selecting which processes are executed and which central processing units are utilized.

Time sharing

Having a single data structure for ready processes that is shared across all of a computer system's processors is the simplest scheduling algorithm for dealing with unrelated processes when using multiprocessors. It could just be a list, but it's more likely to be a collection of lists for the processes with varying levels of importance.

Space Sharing

When there is a close connection between different processes, multiprocessor scheduling can be utilized.

"Space sharing" refers to the practice of coordinating the execution of two or more threads simultaneously across multiple central processing units. The elimination of multi-programming, which eliminates the overhead of context switching, is the primary benefit of using shared space rather than having separate ones.

Gang Scheduling

The following three components make up the gang scheduling system:

Operating System Quiz

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